Intel’s multi-FSB chipsets go back to the future

By Jon Heizer

“While many other high-end processors had multiple buses, scalable SMP interconnects and so on long time ago, alleviating the SMP scaling bottleneck somewhat, Intel still sticks to the old “single clogged FSB” approach. That results in choppy SMP scaling performance even when using CPUs with humungous caches, like the 8 MB XeonMP or 9 MB [...]