Intel’s multi-FSB chipsets go back to the future

By Jon Heizer

“While many other high-end processors had multiple buses, scalable SMP interconnects and so on long time ago, alleviating the SMP scaling bottleneck somewhat, Intel still sticks to the old “single clogged FSB” approach. That results in choppy SMP scaling performance even when using CPUs with humungous caches, like the 8 MB XeonMP or 9 MB Itanium 2. If there wasn’t Opteron, Intel could probably continue like this forever, but, as we all know, Opteron is here and, despite AMD’s sometimes amateurish business attitude, it does, with its superb scaling, steal quite a bit of high-end dough from Intel these days.”

The article continues to talk about the plans Intel has to combact AMD. They also show how Intel’s current plans are similar to Alphas years ago.

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